There may be a new computer chip in the works to handle the “heavy duty load” that is needed for the execution of Internet of Things (IoT) and Big Data tasks.
A team of researchers from the prestigious Stanford University have built a multi-layered “high-rise” chip that could significantly outperform today’s chips. Making this announcement in an article on the University’s News section, Tom Abate writes that the team would be showing off the chip to the world at a conference in San Francisco soon.
Imagine today’s regular chips as busy cities in which logic chips compute and memory chips store data. But when the computer gets busy, the wires connecting logic and memory can get jammed. The Stanford researchers have found a way of getting around these jams.
Their chip has layers of logic atop layers of memory to create a “tightly interconnected high-rise chip.” Many thousands of nanoscale electronic “elevators” would move data between the layers much faster, using less electricity, than the bottleneck-prone wires connecting single-story logic and memory chips today, according to the explanation in the article.
Incidentally, Stanford University has been doing some path-breaking research work in the field of the IoT.
You may want to read this article: Stanford engineers build tiny radio which could link IoT devices
The research work is led by Subhasish Mitra, a Stanford Associate Professor of Electrical Engineering and of Computer Science, and H.-S. Philip Wong, the Williard R. and Inez Kerr Bell Professor in Stanford’s School of Engineering. This work was also done in collaboration with Professors Krishna Saraswat and Yoshio Nishi of Stanford University.
The team has described its new high-rise chip architecture in a paper being presented at the IEEE International Electron Devices Meeting Dec. 15.
The researchers’ innovation leverages three breakthroughs. The first is a new technology for creating transistors, the second is a new type of computer memory that lends itself to multi-story fabrication, while the third is a technique to build these new logic and memory technologies into high-rise structures in a radically different way than previous efforts to stack chips.
Quoting Dr Mitra, the article said the research was at an early stage, but its design and fabrication techniques were scalable.
Image Credit: Stanford University
– Advertising Message –